Fix incorrect TX packet leight

dl9sau
US1GHQ 2022-10-08 19:07:09 +03:00
parent 594b830bcd
commit c11fe57c18
2 changed files with 6 additions and 5 deletions

View File

@ -1,10 +1,10 @@
#ifndef BUILD_NUMBER
#define BUILD_NUMBER "57"
#define BUILD_NUMBER "91"
#endif
#ifndef VERSION
#define VERSION "v0.3.57-290838b - 2022-10-08 15:48:09.958900"
#define VERSION "v0.3.91-290838b - 2022-10-08 18:55:29.826499"
#endif
#ifndef VERSION_SHORT
#define VERSION_SHORT "v0.3.57-290838b"
#define VERSION_SHORT "v0.3.91-290838b"
#endif

View File

@ -384,7 +384,7 @@ int16_t SX127x::startReceive(uint8_t len, uint8_t mode) {
// set expected packet length for SF6
if(_sf == 6) {
state |= _mod->SPIsetRegValue(RADIOLIB_SX127X_REG_PAYLOAD_LENGTH, len + RADIOLIB_SX127X_HEADER_LEN - 1);
state |= _mod->SPIsetRegValue(RADIOLIB_SX127X_REG_PAYLOAD_LENGTH, len);
}
// apply fixes to errata
@ -549,7 +549,7 @@ int16_t SX127x::startTransmit(uint8_t* data, size_t len, uint8_t addr) {
clearIRQFlags();
// set packet length
state |= _mod->SPIsetRegValue(RADIOLIB_SX127X_REG_PAYLOAD_LENGTH, len);
state |= _mod->SPIsetRegValue(RADIOLIB_SX127X_REG_PAYLOAD_LENGTH, len + RADIOLIB_SX127X_HEADER_LEN - 1);
// set FIFO pointers
state |= _mod->SPIsetRegValue(RADIOLIB_SX127X_REG_FIFO_TX_BASE_ADDR, RADIOLIB_SX127X_FIFO_TX_BASE_ADDR_MAX);
@ -584,6 +584,7 @@ int16_t SX127x::startTransmit(uint8_t* data, size_t len, uint8_t addr) {
packetLen = RADIOLIB_SX127X_FIFO_THRESH - 1;
_mod->SPIsetRegValue(RADIOLIB_SX127X_REG_FIFO_THRESH, RADIOLIB_SX127X_TX_START_FIFO_NOT_EMPTY, 7, 7);
}
_mod->SPIwriteRegister(RADIOLIB_SX127X_REG_FIFO, '<');
_mod->SPIwriteRegister(RADIOLIB_SX127X_REG_FIFO, 0xFF);
_mod->SPIwriteRegister(RADIOLIB_SX127X_REG_FIFO, 0x01);