parent
74442ebf12
commit
e6576de2ab
@ -0,0 +1,17 @@
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This software is Copyright (C) Mike McCauley. Use is subject to license
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conditions. The main licensing options available are GPL V3 or Commercial:
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Open Source Licensing GPL V3
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This is the appropriate option if you want to share the source code of your
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application with everyone you distribute it to, and you also want to give them
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the right to share who uses it. If you wish to use this software under Open
|
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Source Licensing, you must contribute all your source code to the open source
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community in accordance with the GPL Version 3 when your application is
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distributed. See http://www.gnu.org/copyleft/gpl.html
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Commercial Licensing
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This is the appropriate option if you are creating proprietary applications
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and you are not prepared to distribute and share the source code of your
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application. Contact info@airspayce for details.
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@ -0,0 +1,196 @@
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RadioHead/LICENSE
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RadioHead/MANIFEST
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RadioHead/project.cfg
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RadioHead/library.properties
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RadioHead/RadioHead.h
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RadioHead/RH_ASK.cpp
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RadioHead/RH_ASK.h
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RadioHead/RH_ABZ.cpp
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RadioHead/RH_ABZ.h
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RadioHead/RHCRC.cpp
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RadioHead/RHCRC.h
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RadioHead/RHDatagram.cpp
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RadioHead/RHDatagram.h
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RadioHead/RHEncryptedDriver.h
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RadioHead/RHEncryptedDriver.cpp
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RadioHead/RHGenericDriver.cpp
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RadioHead/RHGenericDriver.h
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RadioHead/RHGenericSPI.cpp
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RadioHead/RHGenericSPI.h
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RadioHead/RHHardwareSPI.cpp
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RadioHead/RHHardwareSPI.h
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RadioHead/RHMesh.cpp
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RadioHead/RHMesh.h
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RadioHead/RHReliableDatagram.cpp
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RadioHead/RHReliableDatagram.h
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RadioHead/RH_CC110.cpp
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RadioHead/RH_CC110.h
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RadioHead/RH_E32.cpp
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RadioHead/RH_E32.h
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RadioHead/RH_LoRaFileOps.cpp
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RadioHead/RH_LoRaFileOps.h
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RadioHead/RH_NRF24.cpp
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RadioHead/RH_NRF24.h
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RadioHead/RH_NRF51.cpp
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RadioHead/RH_NRF51.h
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RadioHead/RH_NRF905.cpp
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RadioHead/RH_NRF905.h
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RadioHead/RH_RF22.cpp
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RadioHead/RH_RF22.h
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RadioHead/RH_RF24.cpp
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RadioHead/RH_RF24.h
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RadioHead/RH_RF69.cpp
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RadioHead/RH_RF69.h
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RadioHead/RH_MRF89.cpp
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RadioHead/RH_MRF89.h
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RadioHead/RH_RF95.cpp
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RadioHead/RH_RF95.h
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RadioHead/RH_TCP.cpp
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RadioHead/RH_TCP.h
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RadioHead/RHRouter.cpp
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RadioHead/RHRouter.h
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RadioHead/RH_Serial.cpp
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RadioHead/RH_Serial.h
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RadioHead/RHSoftwareSPI.cpp
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RadioHead/RHSoftwareSPI.h
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RadioHead/RHSPIDriver.cpp
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RadioHead/RHSPIDriver.h
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RadioHead/RHTcpProtocol.h
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RadioHead/RHNRFSPIDriver.cpp
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RadioHead/RHNRFSPIDriver.h
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RadioHead/RHutil
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RadioHead/RHutil/atomic.h
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RadioHead/RHutil/simulator.h
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RadioHead/RHutil/HardwareSerial.h
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RadioHead/RHutil/HardwareSerial.cpp
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RadioHead/RHutil/RasPi.cpp
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RadioHead/RHutil/RasPi.h
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RadioHead/RHutil_pigpio/RasPi.cpp
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RadioHead/RHutil_pigpio/RasPi.h
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RadioHead/examples/ask/ask_reliable_datagram_client/ask_reliable_datagram_client.pde
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RadioHead/examples/ask/ask_reliable_datagram_server/ask_reliable_datagram_server.pde
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RadioHead/examples/ask/ask_transmitter/ask_transmitter.pde
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RadioHead/examples/ask/ask_receiver/ask_receiver.pde
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RadioHead/examples/cc110/cc110_client/cc110_client.pde
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RadioHead/examples/cc110/cc110_server/cc110_server.pde
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RadioHead/examples/e32/e32_client/e32_client.pde
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RadioHead/examples/e32/e32_server/e32_server.pde
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RadioHead/examples/abz/abz_client/abz_client.pde
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RadioHead/examples/abz/abz_server/abz_server.pde
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RadioHead/examples/rf95/rf95_client/rf95_client.pde
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RadioHead/examples/rf95/rf95_server/rf95_server.pde
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RadioHead/examples/rf95/rf95_encrypted_client/rf95_encrypted_client.pde
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RadioHead/examples/rf95/rf95_encrypted_server/rf95_encrypted_server.pde
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RadioHead/examples/rf95/rf95_reliable_datagram_client/rf95_reliable_datagram_client.pde
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RadioHead/examples/rf95/rf95_reliable_datagram_server/rf95_reliable_datagram_server.pde
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RadioHead/examples/rf22/rf22_client/rf22_client.pde
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RadioHead/examples/rf22/rf22_mesh_client/rf22_mesh_client.pde
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RadioHead/examples/rf22/rf22_mesh_server1/rf22_mesh_server1.pde
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RadioHead/examples/rf22/rf22_mesh_server2/rf22_mesh_server2.pde
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RadioHead/examples/rf22/rf22_mesh_server3/rf22_mesh_server3.pde
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RadioHead/examples/rf22/rf22_reliable_datagram_client/rf22_reliable_datagram_client.pde
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RadioHead/examples/rf22/rf22_reliable_datagram_server/rf22_reliable_datagram_server.pde
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RadioHead/examples/rf22/rf22_router_client/rf22_router_client.pde
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RadioHead/examples/rf22/rf22_router_server1/rf22_router_server1.pde
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RadioHead/examples/rf22/rf22_router_server2/rf22_router_server2.pde
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RadioHead/examples/rf22/rf22_router_server3/rf22_router_server3.pde
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RadioHead/examples/rf22/rf22_router_test/rf22_router_test.pde
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RadioHead/examples/rf22/rf22_server/rf22_server.pde
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RadioHead/examples/rf22/rf22_cw/rf22_cw.ino
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RadioHead/examples/rf24/rf24_client/rf24_client.pde
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RadioHead/examples/rf24/rf24_lowpower_client/rf24_lowpower_client.pde
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RadioHead/examples/rf24/rf24_reliable_datagram_client/rf24_reliable_datagram_client.pde
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RadioHead/examples/rf24/rf24_reliable_datagram_server/rf24_reliable_datagram_server.pde
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RadioHead/examples/rf24/rf24_server/rf24_server.pde
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RadioHead/examples/rf69/rf69_client/rf69_client.pde
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RadioHead/examples/rf69/rf69_reliable_datagram_client/rf69_reliable_datagram_client.pde
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RadioHead/examples/rf69/rf69_reliable_datagram_server/rf69_reliable_datagram_server.pde
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RadioHead/examples/rf69/rf69_server/rf69_server.pde
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RadioHead/examples/mrf89/mrf89_client/mrf89_client.pde
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RadioHead/examples/mrf89/mrf89_server/mrf89_server.pde
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RadioHead/examples/nrf24/nrf24_client/nrf24_client.pde
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RadioHead/examples/nrf24/nrf24_encrypted_server/nrf24_encrypted_server.pde
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RadioHead/examples/nrf24/nrf24_encrypted_client/nrf24_encrypted_client.pde
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RadioHead/examples/nrf24/nrf24_server/nrf24_server.pde
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RadioHead/examples/nrf24/nrf24_reliable_datagram_client/nrf24_reliable_datagram_client.pde
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RadioHead/examples/nrf24/nrf24_reliable_datagram_server/nrf24_reliable_datagram_server.pde
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RadioHead/examples/nrf51/nrf51_client/nrf51_client.pde
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RadioHead/examples/nrf51/nrf51_reliable_datagram_client/nrf51_reliable_datagram_client.pde
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RadioHead/examples/nrf51/nrf51_reliable_datagram_server/nrf51_reliable_datagram_server.pde
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RadioHead/examples/nrf51/nrf51_server/nrf51_server.pde
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RadioHead/examples/nrf51/nrf51_audio_tx/nrf51_audio_tx.pde
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RadioHead/examples/nrf51/nrf51_audio_tx/nrf51_audio.pdf
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RadioHead/examples/nrf51/nrf51_audio_rx/nrf51_audio_rx.pde
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RadioHead/examples/nrf905/nrf905_client/nrf905_client.pde
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RadioHead/examples/nrf905/nrf905_reliable_datagram_client/nrf905_reliable_datagram_client.pde
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RadioHead/examples/nrf905/nrf905_reliable_datagram_server/nrf905_reliable_datagram_server.pde
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RadioHead/examples/nrf905/nrf905_server/nrf905_server.pde
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RadioHead/examples/serial/serial_reliable_datagram_client/serial_reliable_datagram_client.pde
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RadioHead/examples/serial/serial_reliable_datagram_server/serial_reliable_datagram_server.pde
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RadioHead/examples/serial/serial_gateway/serial_gateway.pde
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RadioHead/examples/simulator/simulator_reliable_datagram_client/simulator_reliable_datagram_client.pde
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RadioHead/examples/simulator/simulator_reliable_datagram_server/simulator_reliable_datagram_server.pde
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RadioHead/examples/raspi/RasPiRH.cpp
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RadioHead/examples/raspi/Makefile
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RadioHead/examples/raspi/rf95/shared
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RadioHead/examples/raspi/rf95/shared/help_functions.h
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RadioHead/examples/raspi/rf95/shared/gpsMT3339.h
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RadioHead/examples/raspi/rf95/shared/help_functions.cpp
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RadioHead/examples/raspi/rf95/shared/gpsMT3339.cpp
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RadioHead/examples/raspi/rf95/rf95_reliable_datagram_client/Makefile
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RadioHead/examples/raspi/rf95/rf95_reliable_datagram_client/rf95_reliable_datagram_client.cpp
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RadioHead/examples/raspi/rf95/rf95_reliable_datagram_server/Makefile
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RadioHead/examples/raspi/rf95/rf95_reliable_datagram_server/rf95_reliable_datagram_server.cpp
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RadioHead/examples/raspi/rf95/rf95_server/Makefile
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RadioHead/examples/raspi/rf95/rf95_server/rf95_server1.cpp
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RadioHead/examples/raspi/rf95/rf95_server/rf95_server2.cpp
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RadioHead/examples/raspi/rf95/rf95_router_test/Makefile
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RadioHead/examples/raspi/rf95/rf95_router_test/rf95_router_test.cpp
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RadioHead/examples/raspi/rf95/rf95_mesh_server3/rf95_mesh_server3.cpp
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RadioHead/examples/raspi/rf95/rf95_mesh_server3/Makefile
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RadioHead/examples/raspi/rf95/rf95_mesh_client/Makefile
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RadioHead/examples/raspi/rf95/rf95_mesh_client/rf95_mesh_client.cpp
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RadioHead/examples/raspi/rf95/rf95_mesh_server2/Makefile
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RadioHead/examples/raspi/rf95/rf95_mesh_server2/rf95_mesh_server2.cpp
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RadioHead/examples/raspi/rf95/rf95_client/Makefile
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RadioHead/examples/raspi/rf95/rf95_client/rf95_client1.cpp
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RadioHead/examples/raspi/rf95/rf95_client/rf95_client2.cpp
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RadioHead/examples/raspi/rf95/rf95_router_client/Makefile
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RadioHead/examples/raspi/rf95/rf95_router_client/rf95_router_client.cpp
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RadioHead/examples/raspi/rf95/rf95_router_server2/Makefile
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RadioHead/examples/raspi/rf95/rf95_router_server2/rf95_router_server2.cpp
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RadioHead/examples/raspi/rf95/rf95_router_server3/rf95_router_server3.cpp
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RadioHead/examples/raspi/rf95/rf95_router_server3/Makefile
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RadioHead/examples/raspi/rf95/rf95_router_server1/rf95_router_server1.cpp
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RadioHead/examples/raspi/rf95/rf95_router_server1/Makefile
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RadioHead/examples/raspi/rf95/rf95_mesh_server1/Makefile
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RadioHead/examples/raspi/rf95/rf95_mesh_server1/rf95_mesh_server1.cpp
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RadioHead/examples/lorafileops/lorafileops_client/lorafileops_client.cpp
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RadioHead/examples/lorafileops/lorafileops_server/lorafileops_server.cpp
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RadioHead/tools/etherSimulator.pl
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RadioHead/tools/chain.conf
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RadioHead/tools/simMain.cpp
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RadioHead/tools/simBuild
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RadioHead/tools/createGPX.pl
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RadioHead/doc
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RadioHead/STM32ArduinoCompat/HardwareSerial.cpp
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RadioHead/STM32ArduinoCompat/HardwareSerial.h
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RadioHead/STM32ArduinoCompat/HardwareSPI.cpp
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RadioHead/STM32ArduinoCompat/HardwareSPI.h
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RadioHead/STM32ArduinoCompat/wirish.cpp
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RadioHead/STM32ArduinoCompat/wirish.h
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RadioHead/STM32ArduinoCompat/README
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RadioHead/RH_RF24_property_data/convert.pl
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RadioHead/RF24configs/radio_config_Si4464_27_434_2GFSK_5_10.h
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RadioHead/RF24configs/radio_config_Si4464_30_915_2GFSK_10_20.h
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RadioHead/RF24configs/radio_config_Si4464_30_434_2GFSK_10_20.h
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RadioHead/RF24configs/radio_config_Si4464_30_915_2GFSK_5_10.h
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RadioHead/RF24configs/radio_config_Si4464_30_434_2GFSK_5_10.h
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RadioHead/RF24configs/README
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RadioHead/MGOSCompat/MGOS.h
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RadioHead/MGOSCompat/HardwareSPI.cpp
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RadioHead/MGOSCompat/MGOS.cpp
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RadioHead/MGOSCompat/HardwareSerial.h
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RadioHead/MGOSCompat/README
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RadioHead/MGOSCompat/HardwareSerial.cpp
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RadioHead/MGOSCompat/HardwareSPI.h
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// ArduinoCompat/HardwareSPI.cpp
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//
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// Interface between Arduino-like SPI interface and STM32F4 Discovery and similar
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// using STM32F4xx_DSP_StdPeriph_Lib_V1.3.0
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#include <RadioHead.h>
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#if (RH_PLATFORM == RH_PLATFORM_MONGOOSE_OS)
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#include <mgos.h>
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#include <mgos_spi.h>
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#include <HardwareSPI.h>
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HardwareSPI::HardwareSPI(uint32_t spiPortNumber) : spiPortNumber(spiPortNumber)
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{
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}
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void HardwareSPI::begin(int frequency, uint32_t bitOrder, uint32_t mode)
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{
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//Set the SPI tx/rx buffer pointers.
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txn.fd.tx_data = spiTXBuf;
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txn.fd.rx_data = spiRXBuf;
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txn.freq = frequency;
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this->bitOrder = bitOrder;
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txn.mode = mode;
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#ifdef RH_USE_SPI
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txn.cs = mgos_sys_config_get_rh_spi_cs();
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#else
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txn.cs = -1;
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#endif
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}
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void HardwareSPI::end(void)
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{
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struct mgos_spi *spi = mgos_spi_get_global();
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mgos_spi_close(spi);
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}
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uint8_t HardwareSPI::reverseBits(uint8_t value)
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{
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value = (value & 0xF0) >> 4 | (value & 0x0F) << 4;
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value = (value & 0xCC) >> 2 | (value & 0x33) << 2;
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value = (value & 0xAA) >> 1 | (value & 0x55) << 1;
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return value;
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}
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uint8_t HardwareSPI::transfer(uint8_t data)
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{
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uint8_t status=0;
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txn.fd.len=1;
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spiTXBuf[0]=data;
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if( bitOrder != MSBFIRST ) {
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spiTXBuf[0]=reverseBits(spiTXBuf[0]);
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}
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bool success = mgos_spi_run_txn( mgos_spi_get_global(), true, &txn);
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if( !success ) {
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LOG(LL_INFO, ("%s: Failed SPI transfer()", __FUNCTION__) );
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}
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status = spiRXBuf[0];
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if( bitOrder != MSBFIRST ) {
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status = reverseBits(status);
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}
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return status;
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}
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uint8_t HardwareSPI::transfer2B(uint8_t byte0, uint8_t byte1)
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{
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uint8_t status=0;
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txn.fd.len=2;
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spiTXBuf[0]=byte0;
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spiTXBuf[1]=byte1;
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if( bitOrder != MSBFIRST ) {
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spiTXBuf[0]=reverseBits(spiTXBuf[0]);
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spiTXBuf[1]=reverseBits(spiTXBuf[1]);
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}
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bool success = mgos_spi_run_txn( mgos_spi_get_global(), true, &txn);
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if( !success ) {
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LOG(LL_INFO, ("%s: Failed SPI transfer()", __FUNCTION__) );
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}
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status = spiRXBuf[0];
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if( bitOrder != MSBFIRST ) {
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status = reverseBits(status);
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}
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return status;
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}
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uint8_t HardwareSPI::spiBurstRead(uint8_t reg, uint8_t* dest, uint8_t len) {
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uint8_t status=0;
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if( len+1 <= SPI_RX_BUFFER_SIZE ) {
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txn.fd.len=len+1;
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memset(spiTXBuf, 0, SPI_RX_BUFFER_SIZE);
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spiTXBuf[0]=reg;
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if( bitOrder != MSBFIRST ) {
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spiTXBuf[0]=reverseBits(spiTXBuf[0]);
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}
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bool success = mgos_spi_run_txn( mgos_spi_get_global(), true, &txn);
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if( !success ) {
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LOG(LL_INFO, ("%s: Failed SPI transfer()", __FUNCTION__) );
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}
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if( bitOrder != MSBFIRST ) {
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uint8_t index=0;
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for( index=0 ; index<len+1 ; index++) {
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spiRXBuf[0]=reverseBits(spiRXBuf[0]);
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}
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}
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memcpy(dest, spiRXBuf+1, len); //copy all but the status byte to the data read buffer
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status = spiRXBuf[0]; //return the status byte
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}
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else {
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LOG(LL_INFO, ("%s: RX buffer not large enough (rx buf length = %d bytes message length = %d bytes).", __FUNCTION__, SPI_RX_BUFFER_SIZE, len) );
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}
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return status;
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}
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uint8_t HardwareSPI::spiBurstWrite(uint8_t reg, const uint8_t* src, uint8_t len) {
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uint8_t status=0;
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txn.fd.len=len+1;
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memcpy(spiTXBuf+1, src, len);
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spiTXBuf[0]=reg;
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if( bitOrder != MSBFIRST ) {
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uint8_t index=0;
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for( index=0 ; index<len+1 ; index++) {
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spiTXBuf[index]=reverseBits(spiTXBuf[index]);
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}
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}
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memset(spiRXBuf, 0, SPI_RX_BUFFER_SIZE);
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bool success = mgos_spi_run_txn( mgos_spi_get_global(), true, &txn);
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if( !success ) {
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||||
LOG(LL_INFO, ("%s: Failed SPI transfer()", __FUNCTION__) );
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||||
}
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||||
status = spiRXBuf[0];
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||||
if( bitOrder != MSBFIRST ) {
|
||||
status = reverseBits(status);
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||||
}
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||||
return status;
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}
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||||
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||||
int8_t HardwareSPI::getCSGpio() {
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uint8_t rhSPICSPin=-1;
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||||
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||||
if( txn.cs == 0 ) {
|
||||
rhSPICSPin = mgos_sys_config_get_spi_cs0_gpio();
|
||||
}
|
||||
else if ( txn.cs == 1 ) {
|
||||
rhSPICSPin = mgos_sys_config_get_spi_cs1_gpio();
|
||||
}
|
||||
else if ( txn.cs == 2 ) {
|
||||
rhSPICSPin = mgos_sys_config_get_spi_cs2_gpio();
|
||||
}
|
||||
return rhSPICSPin;
|
||||
}
|
||||
|
||||
#endif
|
||||
@ -0,0 +1,49 @@
|
||||
// ArduinoCompat/HardwareSPI.h
|
||||
// STM32 implementattion of Arduino compatible SPI class
|
||||
|
||||
#ifndef _HardwareSPI_h
|
||||
#define _HardwareSPI_h
|
||||
#include <mgos.h>
|
||||
#include <mgos_spi.h>
|
||||
#include <stdint.h>
|
||||
|
||||
extern "C"
|
||||
{
|
||||
struct mgos_spi *mgos_spi_get_global(void);
|
||||
bool mgos_spi_run_txn(struct mgos_spi *spi, bool full_duplex, const struct mgos_spi_txn *txn);
|
||||
}
|
||||
|
||||
//Not used on MGOS as SPI config is set in mos.yml
|
||||
#define SPI_MODE0 0x00
|
||||
#define SPI_MODE1 0x01
|
||||
#define SPI_MODE2 0x03
|
||||
#define SPI_MODE3 0x02
|
||||
|
||||
#define SPI_TX_BUFFER_SIZE 64
|
||||
#define SPI_RX_BUFFER_SIZE 64
|
||||
|
||||
class HardwareSPI
|
||||
{
|
||||
public:
|
||||
HardwareSPI(uint32_t spiPortNumber); // Only port SPI1 is currently supported
|
||||
void begin(int frequency, uint32_t bitOrder, uint32_t mode);
|
||||
void end(void);
|
||||
uint8_t reverseBits(uint8_t value);
|
||||
int8_t getCSGpio();
|
||||
uint8_t transfer(uint8_t data);
|
||||
uint8_t transfer2B(uint8_t byte0, uint8_t byte1);
|
||||
uint8_t spiBurstRead(uint8_t reg, uint8_t* dest, uint8_t len);
|
||||
uint8_t spiBurstWrite(uint8_t reg, const uint8_t* src, uint8_t len);
|
||||
private:
|
||||
uint32_t spiPortNumber; // Not used
|
||||
struct mgos_spi_txn txn;
|
||||
uint32_t bitOrder;
|
||||
//Define spi TX and RX buffers.This is a little wasteful of memory
|
||||
//but no dynamic memory allocation fits with the RadioHead library.
|
||||
uint8_t spiTXBuf[SPI_TX_BUFFER_SIZE];
|
||||
uint8_t spiRXBuf[SPI_RX_BUFFER_SIZE];
|
||||
};
|
||||
extern HardwareSPI SPI;
|
||||
|
||||
|
||||
#endif
|
||||
@ -0,0 +1,189 @@
|
||||
// ArduinoCompat/HardwareSerial.cpp
|
||||
//
|
||||
// Author: mikem@airspayce.com
|
||||
|
||||
#include <RadioHead.h>
|
||||
#if (RH_PLATFORM == RH_PLATFORM_MONGOOSE_OS)
|
||||
#include <mgos.h>
|
||||
#include <HardwareSerial.h>
|
||||
|
||||
extern "C" {
|
||||
static inline void mgos_sys_config_set_rh_serial_baud(int v);
|
||||
static inline void mgos_sys_config_set_rh_serial_databits(int v);
|
||||
static inline void mgos_sys_config_set_rh_serial_parity(int v);
|
||||
static inline void mgos_sys_config_set_rh_serial_stopbits(int v);
|
||||
|
||||
void mgos_uart_config_set_defaults(int uart_no, struct mgos_uart_config *cfg);
|
||||
bool mgos_uart_configure(int uart_no, const struct mgos_uart_config *cfg);
|
||||
void mgos_uart_set_rx_enabled(int uart_no, bool enabled);
|
||||
size_t mgos_uart_read_avail(int uart_no);
|
||||
size_t mgos_uart_read(int uart_no, void *buf, size_t len);
|
||||
size_t mgos_uart_write(int uart_no, const void *buf, size_t len);
|
||||
};
|
||||
|
||||
|
||||
// instantiate Serial objects
|
||||
HardwareSerial Serial0(0);
|
||||
HardwareSerial Serial1(1);
|
||||
HardwareSerial Serial2(2);
|
||||
|
||||
/*
|
||||
* Serial ports
|
||||
*
|
||||
* ESP8266
|
||||
* The esp8266 device has two uarts (0 and 1), Uart 1 TX is typically used for debugging. No Uart 1 RX is available on the esp8266.
|
||||
*
|
||||
* Uart 0
|
||||
* RX = GPIO3
|
||||
* TX = GPIO1
|
||||
*
|
||||
* Uart 1
|
||||
* TX = GPIO2
|
||||
*
|
||||
* ESP32
|
||||
* The esp32 device has three uarts (0,1 and 2). Uart 0 is typically used for debugging/loading code.
|
||||
*
|
||||
* Uart 0
|
||||
* RX = GPIO3
|
||||
* TX = GPIO1
|
||||
* CTS = GPIO19
|
||||
* RTS = GPIO22
|
||||
*
|
||||
* Uart 1
|
||||
* RX = GPIO25
|
||||
* TX = GPIO26
|
||||
* CTS = GPIO27
|
||||
* RTS = GPIO13
|
||||
*
|
||||
* Uart 2
|
||||
* RX = GPIO16
|
||||
* TX = GPIO17
|
||||
* CTS = GPIO14
|
||||
* RTS = GPIO15
|
||||
*/
|
||||
|
||||
///////////////////////////////////////////////////////////////
|
||||
// HardwareSerial
|
||||
///////////////////////////////////////////////////////////////
|
||||
|
||||
HardwareSerial::HardwareSerial(int uartIndex)
|
||||
{
|
||||
this->uartIndex=uartIndex;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Init the serial port.
|
||||
* @param baud If the baud rate is 0 or -ve then the persistent sorage value
|
||||
* is used. Starting at the value in mos.yml.
|
||||
*/
|
||||
void HardwareSerial::begin(int baud)
|
||||
{
|
||||
struct mgos_uart_config ucfg;
|
||||
|
||||
if( mgos_sys_config_get_rh_serial_baud() != baud ) {
|
||||
mgos_sys_config_set_rh_serial_baud(baud);
|
||||
}
|
||||
|
||||
mgos_uart_config_set_defaults(this->uartIndex, &ucfg);
|
||||
ucfg.baud_rate = mgos_sys_config_get_rh_serial_baud();
|
||||
ucfg.num_data_bits = mgos_sys_config_get_rh_serial_databits();
|
||||
ucfg.parity = (mgos_uart_parity)mgos_sys_config_get_rh_serial_parity();
|
||||
ucfg.stop_bits = (mgos_uart_stop_bits)mgos_sys_config_get_rh_serial_stopbits();
|
||||
mgos_uart_configure(this->uartIndex, &ucfg);
|
||||
if( mgos_uart_configure(this->uartIndex, &ucfg) ) {
|
||||
mgos_uart_set_rx_enabled(this->uartIndex, true);
|
||||
mgos_uart_set_dispatcher(this->uartIndex, NULL, NULL);
|
||||
}
|
||||
|
||||
#ifdef NO_ESP32_RXD_PULLUP
|
||||
if( this->uartIndex == 0 ) {
|
||||
mgos_gpio_setup_input(3, MGOS_GPIO_PULL_NONE);
|
||||
}
|
||||
else if( this->uartIndex == 1 ) {
|
||||
mgos_gpio_setup_input(25, MGOS_GPIO_PULL_NONE);
|
||||
}
|
||||
else if( this->uartIndex == 2 ) {
|
||||
mgos_gpio_setup_input(16, MGOS_GPIO_PULL_NONE);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
void HardwareSerial::end()
|
||||
{
|
||||
mgos_uart_set_rx_enabled(this->uartIndex, false);
|
||||
}
|
||||
|
||||
int HardwareSerial::available(void)
|
||||
{
|
||||
size_t reqRxByteCount=1;
|
||||
//We have to read the byte because Mongoose OS requires a return
|
||||
//to the RTOS in order to update the value read by mgos_uart_read_avail()
|
||||
rxByteCountAvail = mgos_uart_read(this->uartIndex, &rxByte, reqRxByteCount);
|
||||
return rxByteCountAvail;
|
||||
}
|
||||
|
||||
int HardwareSerial::read(void)
|
||||
{
|
||||
return rxByte;
|
||||
}
|
||||
|
||||
size_t HardwareSerial::write(uint8_t ch)
|
||||
{
|
||||
size_t wr_byte_count = 0;
|
||||
|
||||
wr_byte_count = mgos_uart_write(this->uartIndex, &ch, 1);
|
||||
|
||||
return wr_byte_count;
|
||||
}
|
||||
|
||||
size_t HardwareSerial::print(char ch)
|
||||
{
|
||||
printf("%c", ch);
|
||||
return 0;
|
||||
}
|
||||
|
||||
size_t HardwareSerial::println(char ch)
|
||||
{
|
||||
printf("%c\n", ch);
|
||||
return 0;
|
||||
}
|
||||
|
||||
size_t HardwareSerial::print(unsigned char ch, int base)
|
||||
{
|
||||
if( base == DEC ) {
|
||||
printf("%d", ch);
|
||||
}
|
||||
else if( base == HEX ) {
|
||||
printf("%02x", ch);
|
||||
}
|
||||
else if( base == OCT ) {
|
||||
printf("%o", ch);
|
||||
}
|
||||
//TODO Add binary print
|
||||
return 0;
|
||||
}
|
||||
|
||||
size_t HardwareSerial::println(unsigned char ch, int base)
|
||||
{
|
||||
print((unsigned int)ch, base);
|
||||
printf("\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
size_t HardwareSerial::println(const char* s)
|
||||
{
|
||||
if( s ) {
|
||||
printf("%s\n",s);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
size_t HardwareSerial::print(const char* s)
|
||||
{
|
||||
if( s) {
|
||||
printf(s);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
#endif
|
||||
@ -0,0 +1,49 @@
|
||||
// ArduinoCompat/HardwareSerial.h
|
||||
// Mongoose OS implementation of Arduino compatible serial class
|
||||
|
||||
#include <RadioHead.h>
|
||||
#if (RH_PLATFORM == RH_PLATFORM_MONGOOSE_OS)
|
||||
#ifndef _HardwareSerial_h
|
||||
#define _HardwareSerial_h
|
||||
|
||||
#include <mgos.h>
|
||||
#include <stdint.h>
|
||||
#include <stdio.h>
|
||||
|
||||
// Mostly compatible wuith Arduino HardwareSerial
|
||||
// There is just enough here to support RadioHead RH_Serial
|
||||
class HardwareSerial
|
||||
{
|
||||
public:
|
||||
HardwareSerial(int uart_index);
|
||||
void begin(int baud);
|
||||
void end();
|
||||
virtual int available(void);
|
||||
virtual int read(void);
|
||||
virtual size_t write(uint8_t);
|
||||
inline size_t write(unsigned long n) { return write((uint8_t)n); }
|
||||
inline size_t write(long n) { return write((uint8_t)n); }
|
||||
inline size_t write(unsigned int n) { return write((uint8_t)n); }
|
||||
inline size_t write(int n) { return write((uint8_t)n); }
|
||||
|
||||
//These methods will send debug info on the debug serial port (if enabled)
|
||||
size_t println(unsigned char ch, int base);
|
||||
size_t print(unsigned char ch, int base);
|
||||
size_t println(const char ch);
|
||||
size_t print(const char ch);
|
||||
size_t println(const char* s);
|
||||
size_t print(const char* s);
|
||||
|
||||
private:
|
||||
int uartIndex;
|
||||
size_t rxByteCountAvail;
|
||||
uint8_t rxByte;
|
||||
};
|
||||
|
||||
extern HardwareSerial Serial0;
|
||||
extern HardwareSerial Serial1;
|
||||
extern HardwareSerial Serial2;
|
||||
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@ -0,0 +1,159 @@
|
||||
// RasPi.cpp
|
||||
//
|
||||
// Routines for implementing RadioHead on Raspberry Pi
|
||||
// using BCM2835 library for GPIO
|
||||
//
|
||||
// Contributed by Mike Poublon and used with permission
|
||||
|
||||
|
||||
#include <RadioHead.h>
|
||||
|
||||
#if (RH_PLATFORM == RH_PLATFORM_MONGOOSE_OS)
|
||||
|
||||
#include "mgos.h"
|
||||
|
||||
int pwmFreq = 1000;
|
||||
float pwmDutyCycle = 0.5;
|
||||
|
||||
/**
|
||||
* @brief Set the direction of a GPIO pin.
|
||||
* @param pin the Pin whose direction is to be set.
|
||||
* @param mode The direction of the pin (OUTPUT or INPUT)
|
||||
**/
|
||||
void pinMode(uint8_t pin, WiringPinMode mode)
|
||||
{
|
||||
|
||||
//SPI CS GPIO controlled by MGOS lib call so don't allow it to be set here
|
||||
if( SPI.getCSGpio() != pin ) {
|
||||
if (mode == OUTPUT)
|
||||
{
|
||||
mgos_gpio_set_mode(pin, MGOS_GPIO_MODE_OUTPUT);
|
||||
}
|
||||
else if (mode == OUTPUT_OPEN_DRAIN)
|
||||
{
|
||||
mgos_gpio_set_pull(pin, MGOS_GPIO_PULL_UP);
|
||||
mgos_gpio_set_mode(pin, MGOS_GPIO_MODE_OUTPUT);
|
||||
}
|
||||
else if (mode == INPUT || mode == INPUT_FLOATING )
|
||||
{
|
||||
mgos_gpio_set_mode(pin, MGOS_GPIO_MODE_INPUT);
|
||||
}
|
||||
else if (mode == INPUT_ANALOG)
|
||||
{
|
||||
mgos_adc_enable(pin);
|
||||
}
|
||||
else if (mode == INPUT_PULLUP)
|
||||
{
|
||||
mgos_gpio_set_pull(pin, MGOS_GPIO_PULL_UP);
|
||||
mgos_gpio_set_mode(pin, MGOS_GPIO_MODE_INPUT);
|
||||
}
|
||||
else if (mode == INPUT_PULLDOWN)
|
||||
{
|
||||
mgos_gpio_set_pull(pin, MGOS_GPIO_PULL_DOWN);
|
||||
mgos_gpio_set_mode(pin, MGOS_GPIO_MODE_INPUT);
|
||||
}
|
||||
else if (mode == PWM)
|
||||
{
|
||||
mgos_pwm_set(pin, pwmFreq, pwmDutyCycle);
|
||||
}
|
||||
else if (mode == PWM_OPEN_DRAIN) {
|
||||
mgos_pwm_set(pin, pwmFreq, pwmDutyCycle);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the state of a GPIO pin.
|
||||
* @param pin the Pin whose state is to be set.
|
||||
* @param value The state of the pin.
|
||||
*/
|
||||
void digitalWrite(unsigned char pin, unsigned char value)
|
||||
{
|
||||
|
||||
//SPI CS GPIO controlled by MGOS lib call so don't allow it to be set here
|
||||
if( SPI.getCSGpio() != pin ) {
|
||||
mgos_gpio_write(pin,value);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Read the state of a GPIO pin.
|
||||
* @param pin the Pin whose state is to be set.
|
||||
* @return 1 If high, 0 if low.
|
||||
*/
|
||||
uint8_t digitalRead(uint8_t pin)
|
||||
{
|
||||
uint8_t pinState=0;
|
||||
//SPI CS GPIO controlled by MGOS lib call so don't allow it to be set here
|
||||
if( SPI.getCSGpio() != pin ) {
|
||||
pinState = (uint8_t)mgos_gpio_read(pin);
|
||||
}
|
||||
return pinState;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get the number of elapsed milliseconds since the last boot.
|
||||
*/
|
||||
uint32_t millis(void)
|
||||
{
|
||||
return (uint32_t)mgos_uptime_micros()/1000;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Provide a delay in milliseconds.
|
||||
* @param ms The number of Milli Seconds to delay.
|
||||
*/
|
||||
void delay (unsigned long ms)
|
||||
{
|
||||
mgos_msleep(ms);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Generate a random number between limits.
|
||||
* @param min The minimum random value to be generated.
|
||||
* @param max The maximum random value to be generated.
|
||||
*/
|
||||
long random(long min, long max)
|
||||
{
|
||||
return mgos_rand_range( (float)min, (float)max);
|
||||
}
|
||||
|
||||
static void mgos_gpio_int_handler(int pin, void *arg) {
|
||||
void (*handler)(void) = (void (*)())arg;
|
||||
//Note that this handler is executed in interrupt context (ISR)
|
||||
//therefore ensure that actions performed here are acceptable for the
|
||||
//platform on which the code will execute.
|
||||
//E.G
|
||||
//Use of the LOG macro to send debug data on the serial port crashes
|
||||
//esp8266 and esp32 code.
|
||||
handler();
|
||||
(void) pin;
|
||||
(void) arg;
|
||||
}
|
||||
|
||||
void attachInterrupt(uint8_t pin, void (*handler)(void), int rh_mode)
|
||||
{
|
||||
mgos_gpio_int_mode mgos_mode = MGOS_GPIO_INT_NONE;
|
||||
if( rh_mode == CHANGE ) {
|
||||
mgos_mode = MGOS_GPIO_INT_EDGE_ANY;
|
||||
} else if( rh_mode == FALLING ) {
|
||||
mgos_mode = MGOS_GPIO_INT_EDGE_NEG;
|
||||
} else if( rh_mode == RISING ) {
|
||||
mgos_mode = MGOS_GPIO_INT_EDGE_POS;
|
||||
}
|
||||
mgos_gpio_set_int_handler_isr((int)pin, mgos_mode, mgos_gpio_int_handler, (void*)handler);
|
||||
}
|
||||
|
||||
void enableInterupt(uint8_t pin) {
|
||||
mgos_gpio_enable_int(pin);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Perform functions that under Mongoose OS we would normally return
|
||||
* to the RTOS. E,G flush the TX UART buffer.
|
||||
*/
|
||||
void mgosYield(void) {
|
||||
mgos_uart_flush(RH_SERIAL_PORT);
|
||||
}
|
||||
|
||||
#endif
|
||||
@ -0,0 +1,101 @@
|
||||
// MGOS.h
|
||||
//
|
||||
// Routines for implementing RadioHead when using Mongoose OS
|
||||
// see https://mongoose-os.com/mos.html for H/W support when using Mongoose OS
|
||||
// Contributed by Paul Austen
|
||||
|
||||
#ifndef MGOS_h
|
||||
#define MGOS_h
|
||||
|
||||
#define PROGMEM
|
||||
#define memcpy_P memcpy
|
||||
|
||||
#define DEC 10
|
||||
#define HEX 16
|
||||
#define OCT 8
|
||||
#define BIN 2
|
||||
|
||||
#define HIGH 0x1
|
||||
#define LOW 0x0
|
||||
|
||||
#define LSBFIRST 0
|
||||
#define MSBFIRST 1
|
||||
|
||||
#define CHANGE 1
|
||||
#define FALLING 2
|
||||
#define RISING 3
|
||||
|
||||
typedef enum WiringPinMode {
|
||||
OUTPUT, /**< Basic digital output: when the pin is HIGH, the
|
||||
voltage is held at +3.3v (Vcc) and when it is LOW, it
|
||||
is pulled down to ground. */
|
||||
|
||||
OUTPUT_OPEN_DRAIN, /**< In open drain mode, the pin indicates
|
||||
"low" by accepting current flow to ground
|
||||
and "high" by providing increased
|
||||
impedance. An example use would be to
|
||||
connect a pin to a bus line (which is pulled
|
||||
up to a positive voltage by a separate
|
||||
supply through a large resistor). When the
|
||||
pin is high, not much current flows through
|
||||
to ground and the line stays at positive
|
||||
voltage; when the pin is low, the bus
|
||||
"drains" to ground with a small amount of
|
||||
current constantly flowing through the large
|
||||
resistor from the external supply. In this
|
||||
mode, no current is ever actually sourced
|
||||
from the pin. */
|
||||
|
||||
INPUT, /**< Basic digital input. The pin voltage is sampled; when
|
||||
it is closer to 3.3v (Vcc) the pin status is high, and
|
||||
when it is closer to 0v (ground) it is low. If no
|
||||
external circuit is pulling the pin voltage to high or
|
||||
low, it will tend to randomly oscillate and be very
|
||||
sensitive to noise (e.g., a breath of air across the pin
|
||||
might cause the state to flip). */
|
||||
|
||||
INPUT_ANALOG, /**< This is a special mode for when the pin will be
|
||||
used for analog (not digital) reads. Enables ADC
|
||||
conversion to be performed on the voltage at the
|
||||
pin. */
|
||||
|
||||
INPUT_PULLUP, /**< The state of the pin in this mode is reported
|
||||
the same way as with INPUT, but the pin voltage
|
||||
is gently "pulled up" towards +3.3v. This means
|
||||
the state will be high unless an external device
|
||||
is specifically pulling the pin down to ground,
|
||||
in which case the "gentle" pull up will not
|
||||
affect the state of the input. */
|
||||
|
||||
INPUT_PULLDOWN, /**< The state of the pin in this mode is reported
|
||||
the same way as with INPUT, but the pin voltage
|
||||
is gently "pulled down" towards 0v. This means
|
||||
the state will be low unless an external device
|
||||
is specifically pulling the pin up to 3.3v, in
|
||||
which case the "gentle" pull down will not
|
||||
affect the state of the input. */
|
||||
|
||||
INPUT_FLOATING, /**< Synonym for INPUT. */
|
||||
|
||||
PWM, /**< This is a special mode for when the pin will be used for
|
||||
PWM output (a special case of digital output). */
|
||||
|
||||
PWM_OPEN_DRAIN, /**< Like PWM, except that instead of alternating
|
||||
cycles of LOW and HIGH, the voltage on the pin
|
||||
consists of alternating cycles of LOW and
|
||||
floating (disconnected). */
|
||||
} WiringPinMode;
|
||||
|
||||
extern "C" {
|
||||
void pinMode(uint8_t pin, WiringPinMode mode);
|
||||
void digitalWrite(unsigned char pin, unsigned char value);
|
||||
uint8_t digitalRead(uint8_t pin);
|
||||
uint32_t millis(void);
|
||||
void delay (unsigned long ms);
|
||||
long random(long min, long max);
|
||||
void attachInterrupt(uint8_t pin, void (*handler)(void), int rh_mode);
|
||||
void mgosYield(void);
|
||||
void enableInterupt(uint8_t pin);
|
||||
}
|
||||
|
||||
#endif
|
||||
@ -0,0 +1 @@
|
||||
This directory contains some files to allow RadioHead to be built on Mongoose OS.
|
||||
@ -0,0 +1,19 @@
|
||||
This directory contains a selection of radio configuiration files for use by RH_RF24.cpp
|
||||
They were generated by Silicon Labs Wireless Development Suite (WDS) 3.2.11.0
|
||||
The configuration file controls all the basic frequency aand modulation parameters for the radio.
|
||||
The appropriate one for your application or sketch must be #included by RH_RF24.cpp
|
||||
|
||||
You can generate your own custom configuration file by generatng a new one with WDS,
|
||||
copying it to this directory with a unique anme and #include it in RH_RF24.cpp
|
||||
|
||||
The file names encode the basic parameters:
|
||||
|
||||
radio_config_Siaaaa_bb_ccc_dddd_ee_ff_gg.h
|
||||
|
||||
where
|
||||
aaaa = Chip typenukber eg 4464
|
||||
bb = Crytsyal frequency in MHz
|
||||
ccc = RF base frequency in MHz
|
||||
dddd = Modulation type eg 2GFSK
|
||||
ee = Data rate in kbps
|
||||
ff = Deviation in kHz
|
||||
@ -0,0 +1,516 @@
|
||||
/*! @file radio_config.h
|
||||
* @brief This file contains the automatically generated
|
||||
* configurations.
|
||||
*
|
||||
* @n WDS GUI Version: 3.2.11.0
|
||||
* @n Device: Si4464 Rev.: B1
|
||||
*
|
||||
* @b COPYRIGHT
|
||||
* @n Silicon Laboratories Confidential
|
||||
* @n Copyright 2017 Silicon Laboratories, Inc.
|
||||
* @n http://www.silabs.com
|
||||
*/
|
||||
|
||||
#ifndef RADIO_CONFIG_H_
|
||||
#define RADIO_CONFIG_H_
|
||||
|
||||
// USER DEFINED PARAMETERS
|
||||
// Define your own parameters here
|
||||
|
||||
// INPUT DATA
|
||||
/*
|
||||
// Crys_freq(Hz): 27000000 Crys_tol(ppm): 20 IF_mode: 2 High_perf_Ch_Fil: 1 OSRtune: 0 Ch_Fil_Bw_AFC: 0 ANT_DIV: 0 PM_pattern: 0
|
||||
// MOD_type: 3 Rsymb(sps): 5000 Fdev(Hz): 10000 RXBW(Hz): 150000 Manchester: 0 AFC_en: 0 Rsymb_error: 0.0 Chip-Version: 3
|
||||
// RF Freq.(MHz): 434 API_TC: 29 fhst: 250000 inputBW: 0 BERT: 0 RAW_dout: 0 D_source: 0 Hi_pfm_div: 1
|
||||
//
|
||||
// # RX IF frequency is -421875 Hz
|
||||
// # WB filter 2 (BW = 61.84 kHz); NB-filter 2 (BW = 61.84 kHz)
|
||||
//
|
||||
// Modulation index: 4
|
||||
*/
|
||||
|
||||
|
||||
// CONFIGURATION PARAMETERS
|
||||
#define RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ 27000000L
|
||||
#define RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER 0x00
|
||||
#define RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH 0x07
|
||||
#define RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP 0x03
|
||||
#define RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET 0xF000
|
||||
|
||||
|
||||
// CONFIGURATION COMMANDS
|
||||
|
||||
/*
|
||||
// Command: RF_POWER_UP
|
||||
// Description: Command to power-up the device and select the operational mode and functionality.
|
||||
*/
|
||||
#define RF_POWER_UP 0x02, 0x01, 0x00, 0x01, 0x9B, 0xFC, 0xC0
|
||||
|
||||
/*
|
||||
// Command: RF_GPIO_PIN_CFG
|
||||
// Description: Configures the GPIO pins.
|
||||
*/
|
||||
#define RF_GPIO_PIN_CFG 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
|
||||
|
||||
/*
|
||||
// Set properties: RF_GLOBAL_XO_TUNE_2
|
||||
// Number of properties: 2
|
||||
// Group ID: 0x00
|
||||
// Start ID: 0x00
|
||||
// Default values: 0x40, 0x00,
|
||||
// Descriptions:
|
||||
// GLOBAL_XO_TUNE - Configure the internal capacitor frequency tuning bank for the crystal oscillator.
|
||||
// GLOBAL_CLK_CFG - Clock configuration options.
|
||||
*/
|
||||
#define RF_GLOBAL_XO_TUNE_2 0x11, 0x00, 0x02, 0x00, 0x52, 0x00
|
||||
|
||||
/*
|
||||
// Set properties: RF_GLOBAL_CONFIG_1
|
||||
// Number of properties: 1
|
||||
// Group ID: 0x00
|
||||
// Start ID: 0x03
|
||||
// Default values: 0x20,
|
||||
// Descriptions:
|
||||
// GLOBAL_CONFIG - Global configuration settings.
|
||||
*/
|
||||
#define RF_GLOBAL_CONFIG_1 0x11, 0x00, 0x01, 0x03, 0x60
|
||||
|
||||
/*
|
||||
// Set properties: RF_INT_CTL_ENABLE_2
|
||||
// Number of properties: 2
|
||||
// Group ID: 0x01
|
||||
// Start ID: 0x00
|
||||
// Default values: 0x04, 0x00,
|
||||
// Descriptions:
|
||||
// INT_CTL_ENABLE - This property provides for global enabling of the three interrupt groups (Chip, Modem and Packet Handler) in order to generate HW interrupts at the NIRQ pin.
|
||||
// INT_CTL_PH_ENABLE - Enable individual interrupt sources within the Packet Handler Interrupt Group to generate a HW interrupt on the NIRQ output pin.
|
||||
*/
|
||||
#define RF_INT_CTL_ENABLE_2 0x11, 0x01, 0x02, 0x00, 0x01, 0x20
|
||||
|
||||
/*
|
||||
// Set properties: RF_FRR_CTL_A_MODE_4
|
||||
// Number of properties: 4
|
||||
// Group ID: 0x02
|
||||
// Start ID: 0x00
|
||||
// Default values: 0x01, 0x02, 0x09, 0x00,
|
||||
// Descriptions:
|
||||
// FRR_CTL_A_MODE - Fast Response Register A Configuration.
|
||||
// FRR_CTL_B_MODE - Fast Response Register B Configuration.
|
||||
// FRR_CTL_C_MODE - Fast Response Register C Configuration.
|
||||
// FRR_CTL_D_MODE - Fast Response Register D Configuration.
|
||||
*/
|
||||
#define RF_FRR_CTL_A_MODE_4 0x11, 0x02, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00
|
||||
|
||||
/*
|
||||
// Set properties: RF_PREAMBLE_TX_LENGTH_1
|
||||
// Number of properties: 1
|
||||
// Group ID: 0x10
|
||||
// Start ID: 0x00
|
||||
// Default values: 0x08,
|
||||
// Descriptions:
|
||||
// PREAMBLE_TX_LENGTH - Configure length of TX Preamble.
|
||||
*/
|
||||
#define RF_PREAMBLE_TX_LENGTH_1 0x11, 0x10, 0x01, 0x00, 0x0A
|
||||
|
||||
/*
|
||||
// Set properties: RF_PREAMBLE_CONFIG_1
|
||||
// Number of properties: 1
|
||||
// Group ID: 0x10
|
||||
// Start ID: 0x04
|
||||
// Default values: 0x21,
|
||||
// Descriptions:
|
||||
// PREAMBLE_CONFIG - General configuration bits for the Preamble field.
|
||||
*/
|
||||
#define RF_PREAMBLE_CONFIG_1 0x11, 0x10, 0x01, 0x04, 0x31
|
||||
|
||||
/*
|
||||
// Set properties: RF_SYNC_CONFIG_3
|
||||
// Number of properties: 3
|
||||
// Group ID: 0x11
|
||||
// Start ID: 0x00
|
||||
// Default values: 0x01, 0x2D, 0xD4,
|
||||
// Descriptions:
|
||||
// SYNC_CONFIG - Sync Word configuration bits.
|
||||
// SYNC_BITS_31_24 - Sync word.
|
||||
// SYNC_BITS_23_16 - Sync word.
|
||||
*/
|
||||
#define RF_SYNC_CONFIG_3 0x11, 0x11, 0x03, 0x00, 0x01, 0xB4, 0x2B
|
||||
|
||||
/*
|
||||
// Set properties: RF_PKT_CONFIG1_1
|
||||
// Number of properties: 1
|
||||
// Group ID: 0x12
|
||||
// Start ID: 0x06
|
||||
// Default values: 0x00,
|
||||
// Descriptions:
|
||||
// PKT_CONFIG1 - General configuration bits for transmission or reception of a packet.
|
||||
*/
|
||||
#define RF_PKT_CONFIG1_1 0x11, 0x12, 0x01, 0x06, 0x02
|
||||
|
||||
/*
|
||||
// Set properties: RF_PKT_FIELD_1_CONFIG_1
|
||||
// Number of properties: 1
|
||||
// Group ID: 0x12
|
||||
// Start ID: 0x0F
|
||||
// Default values: 0x00,
|
||||
// Descriptions:
|
||||
// PKT_FIELD_1_CONFIG - General data processing and packet configuration bits for Field 1.
|
||||
*/
|
||||
#define RF_PKT_FIELD_1_CONFIG_1 0x11, 0x12, 0x01, 0x0F, 0x04
|
||||
|
||||
/*
|
||||
// Set properties: RF_MODEM_MOD_TYPE_12
|
||||
// Number of properties: 12
|
||||
// Group ID: 0x20
|
||||
// Start ID: 0x00
|
||||
// Default values: 0x02, 0x80, 0x07, 0x0F, 0x42, 0x40, 0x01, 0xC9, 0xC3, 0x80, 0x00, 0x06,
|
||||
// Descriptions:
|
||||
// MODEM_MOD_TYPE - Selects the type of modulation. In TX mode, additionally selects the source of the modulation.
|
||||
// MODEM_MAP_CONTROL - Controls polarity and mapping of transmit and receive bits.
|
||||
// MODEM_DSM_CTRL - Miscellaneous control bits for the Delta-Sigma Modulator (DSM) in the PLL Synthesizer.
|
||||
// MODEM_DATA_RATE_2 - Unsigned 24-bit value used to determine the TX data rate
|
||||
// MODEM_DATA_RATE_1 - Unsigned 24-bit value used to determine the TX data rate
|
||||
// MODEM_DATA_RATE_0 - Unsigned 24-bit value used to determine the TX data rate
|
||||
// MODEM_TX_NCO_MODE_3 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
|
||||
// MODEM_TX_NCO_MODE_2 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
|
||||
// MODEM_TX_NCO_MODE_1 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
|
||||
// MODEM_TX_NCO_MODE_0 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
|
||||
// MODEM_FREQ_DEV_2 - 17-bit unsigned TX frequency deviation word.
|
||||
// MODEM_FREQ_DEV_1 - 17-bit unsigned TX frequency deviation word.
|
||||
*/
|
||||
#define RF_MODEM_MOD_TYPE_12 0x11, 0x20, 0x0C, 0x00, 0x03, 0x00, 0x07, 0x03, 0x0D, 0x40, 0x05, 0x9B, 0xFC, 0xC0, 0x00, 0x03
|
||||
|
||||
/*
|
||||
// Set properties: RF_MODEM_FREQ_DEV_0_1
|
||||
// Number of properties: 1
|
||||
// Group ID: 0x20
|
||||
// Start ID: 0x0C
|
||||
// Default values: 0xD3,
|
||||
// Descriptions:
|
||||
// MODEM_FREQ_DEV_0 - 17-bit unsigned TX frequency deviation word.
|
||||
*/
|
||||
#define RF_MODEM_FREQ_DEV_0_1 0x11, 0x20, 0x01, 0x0C, 0x09
|
||||
|
||||
/*
|
||||
// Set properties: RF_MODEM_TX_RAMP_DELAY_8
|
||||
// Number of properties: 8
|
||||
// Group ID: 0x20
|
||||
// Start ID: 0x18
|
||||
// Default values: 0x01, 0x00, 0x08, 0x03, 0xC0, 0x00, 0x10, 0x20,
|
||||
// Descriptions:
|
||||
// MODEM_TX_RAMP_DELAY - TX ramp-down delay setting.
|
||||
// MODEM_MDM_CTRL - MDM control.
|
||||
// MODEM_IF_CONTROL - Selects Fixed-IF, Scaled-IF, or Zero-IF mode of RX Modem operation.
|
||||
// MODEM_IF_FREQ_2 - the IF frequency setting (an 18-bit signed number).
|
||||
// MODEM_IF_FREQ_1 - the IF frequency setting (an 18-bit signed number).
|
||||
// MODEM_IF_FREQ_0 - the IF frequency setting (an 18-bit signed number).
|
||||
// MODEM_DECIMATION_CFG1 - Specifies three decimator ratios for the Cascaded Integrator Comb (CIC) filter.
|
||||
// MODEM_DECIMATION_CFG0 - Specifies miscellaneous parameters and decimator ratios for the Cascaded Integrator Comb (CIC) filter.
|
||||
*/
|
||||
#define RF_MODEM_TX_RAMP_DELAY_8 0x11, 0x20, 0x08, 0x18, 0x01, 0x80, 0x08, 0x03, 0x80, 0x00, 0x20, 0x10
|
||||
|
||||
/*
|
||||
// Set properties: RF_MODEM_BCR_OSR_1_9
|
||||
// Number of properties: 9
|
||||
// Group ID: 0x20
|
||||
// Start ID: 0x22
|
||||
// Default values: 0x00, 0x4B, 0x06, 0xD3, 0xA0, 0x06, 0xD3, 0x02, 0xC0,
|
||||
// Descriptions:
|
||||
// MODEM_BCR_OSR_1 - RX BCR/Slicer oversampling rate (12-bit unsigned number).
|
||||
// MODEM_BCR_OSR_0 - RX BCR/Slicer oversampling rate (12-bit unsigned number).
|
||||
// MODEM_BCR_NCO_OFFSET_2 - RX BCR NCO offset value (an unsigned 22-bit number).
|
||||
// MODEM_BCR_NCO_OFFSET_1 - RX BCR NCO offset value (an unsigned 22-bit number).
|
||||
// MODEM_BCR_NCO_OFFSET_0 - RX BCR NCO offset value (an unsigned 22-bit number).
|
||||
// MODEM_BCR_GAIN_1 - The unsigned 11-bit RX BCR loop gain value.
|
||||
// MODEM_BCR_GAIN_0 - The unsigned 11-bit RX BCR loop gain value.
|
||||
// MODEM_BCR_GEAR - RX BCR loop gear control.
|
||||
// MODEM_BCR_MISC1 - Miscellaneous control bits for the RX BCR loop.
|
||||
*/
|
||||
#define RF_MODEM_BCR_OSR_1_9 0x11, 0x20, 0x09, 0x22, 0x01, 0xC2, 0x01, 0x23, 0x45, 0x00, 0x92, 0x02, 0xC2
|
||||
|
||||
/*
|
||||
// Set properties: RF_MODEM_AFC_GEAR_7
|
||||
// Number of properties: 7
|
||||
// Group ID: 0x20
|
||||
// Start ID: 0x2C
|
||||
// Default values: 0x00, 0x23, 0x83, 0x69, 0x00, 0x40, 0xA0,
|
||||
// Descriptions:
|
||||
// MODEM_AFC_GEAR - RX AFC loop gear control.
|
||||
// MODEM_AFC_WAIT - RX AFC loop wait time control.
|
||||
// MODEM_AFC_GAIN_1 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality.
|
||||
// MODEM_AFC_GAIN_0 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality.
|
||||
// MODEM_AFC_LIMITER_1 - Set the AFC limiter value.
|
||||
// MODEM_AFC_LIMITER_0 - Set the AFC limiter value.
|
||||
// MODEM_AFC_MISC - Specifies miscellaneous AFC control bits.
|
||||
*/
|
||||
#define RF_MODEM_AFC_GEAR_7 0x11, 0x20, 0x07, 0x2C, 0x04, 0x36, 0x80, 0x10, 0x18, 0x36, 0x80
|
||||
|
||||
/*
|
||||
// Set properties: RF_MODEM_AGC_CONTROL_1
|
||||
// Number of properties: 1
|
||||
// Group ID: 0x20
|
||||
// Start ID: 0x35
|
||||
// Default values: 0xE0,
|
||||
// Descriptions:
|
||||
// MODEM_AGC_CONTROL - Miscellaneous control bits for the Automatic Gain Control (AGC) function in the RX Chain.
|
||||
*/
|
||||
#define RF_MODEM_AGC_CONTROL_1 0x11, 0x20, 0x01, 0x35, 0xE2
|
||||
|
||||
/*
|
||||
// Set properties: RF_MODEM_AGC_WINDOW_SIZE_9
|
||||
// Number of properties: 9
|
||||
// Group ID: 0x20
|
||||
// Start ID: 0x38
|
||||
// Default values: 0x11, 0x10, 0x10, 0x0B, 0x1C, 0x40, 0x00, 0x00, 0x2B,
|
||||
// Descriptions:
|
||||
// MODEM_AGC_WINDOW_SIZE - Specifies the size of the measurement and settling windows for the AGC algorithm.
|
||||
// MODEM_AGC_RFPD_DECAY - Sets the decay time of the RF peak detectors.
|
||||
// MODEM_AGC_IFPD_DECAY - Sets the decay time of the IF peak detectors.
|
||||
// MODEM_FSK4_GAIN1 - Specifies the gain factor of the secondary branch in 4(G)FSK ISI-suppression.
|
||||
// MODEM_FSK4_GAIN0 - Specifies the gain factor of the primary branch in 4(G)FSK ISI-suppression.
|
||||
// MODEM_FSK4_TH1 - 16 bit 4(G)FSK slicer threshold.
|
||||
// MODEM_FSK4_TH0 - 16 bit 4(G)FSK slicer threshold.
|
||||
// MODEM_FSK4_MAP - 4(G)FSK symbol mapping code.
|
||||
// MODEM_OOK_PDTC - Configures the attack and decay times of the OOK Peak Detector.
|
||||
*/
|
||||
#define RF_MODEM_AGC_WINDOW_SIZE_9 0x11, 0x20, 0x09, 0x38, 0x11, 0x62, 0x62, 0x00, 0x1A, 0xFF, 0xFF, 0x00, 0x2A
|
||||
|
||||
/*
|
||||
// Set properties: RF_MODEM_OOK_CNT1_8
|
||||
// Number of properties: 8
|
||||
// Group ID: 0x20
|
||||
// Start ID: 0x42
|
||||
// Default values: 0xA4, 0x03, 0x56, 0x02, 0x00, 0xA3, 0x02, 0x80,
|
||||
// Descriptions:
|
||||
// MODEM_OOK_CNT1 - OOK control.
|
||||
// MODEM_OOK_MISC - Selects the detector(s) used for demodulation of an OOK signal, or for demodulation of a (G)FSK signal when using the asynchronous demodulator.
|
||||
// MODEM_RAW_SEARCH - Defines and controls the search period length for the Moving Average and Min-Max detectors.
|
||||
// MODEM_RAW_CONTROL - Defines gain and enable controls for raw / nonstandard mode.
|
||||
// MODEM_RAW_EYE_1 - 11 bit eye-open detector threshold.
|
||||
// MODEM_RAW_EYE_0 - 11 bit eye-open detector threshold.
|
||||
// MODEM_ANT_DIV_MODE - Antenna diversity mode settings.
|
||||
// MODEM_ANT_DIV_CONTROL - Specifies controls for the Antenna Diversity algorithm.
|
||||
*/
|
||||
#define RF_MODEM_OOK_CNT1_8 0x11, 0x20, 0x08, 0x42, 0xA4, 0x02, 0xD6, 0x83, 0x00, 0x90, 0x01, 0x80
|
||||
|
||||
/*
|
||||
// Set properties: RF_MODEM_RSSI_COMP_1
|
||||
// Number of properties: 1
|
||||
// Group ID: 0x20
|
||||
// Start ID: 0x4E
|
||||
// Default values: 0x32,
|
||||
// Descriptions:
|
||||
// MODEM_RSSI_COMP - RSSI compensation value.
|
||||
*/
|
||||
#define RF_MODEM_RSSI_COMP_1 0x11, 0x20, 0x01, 0x4E, 0x40
|
||||
|
||||
/*
|
||||
// Set properties: RF_MODEM_CLKGEN_BAND_1
|
||||
// Number of properties: 1
|
||||
// Group ID: 0x20
|
||||
// Start ID: 0x51
|
||||
// Default values: 0x08,
|
||||
// Descriptions:
|
||||
// MODEM_CLKGEN_BAND - Select PLL Synthesizer output divider ratio as a function of frequency band.
|
||||
*/
|
||||
#define RF_MODEM_CLKGEN_BAND_1 0x11, 0x20, 0x01, 0x51, 0x0A
|
||||
|
||||
/*
|
||||
// Set properties: RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12
|
||||
// Number of properties: 12
|
||||
// Group ID: 0x21
|
||||
// Start ID: 0x00
|
||||
// Default values: 0xFF, 0xBA, 0x0F, 0x51, 0xCF, 0xA9, 0xC9, 0xFC, 0x1B, 0x1E, 0x0F, 0x01,
|
||||
// Descriptions:
|
||||
// MODEM_CHFLT_RX1_CHFLT_COE13_7_0 - Filter coefficients for the first set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX1_CHFLT_COE12_7_0 - Filter coefficients for the first set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX1_CHFLT_COE11_7_0 - Filter coefficients for the first set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX1_CHFLT_COE10_7_0 - Filter coefficients for the first set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX1_CHFLT_COE9_7_0 - Filter coefficients for the first set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX1_CHFLT_COE8_7_0 - Filter coefficients for the first set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX1_CHFLT_COE7_7_0 - Filter coefficients for the first set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX1_CHFLT_COE6_7_0 - Filter coefficients for the first set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX1_CHFLT_COE5_7_0 - Filter coefficients for the first set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX1_CHFLT_COE4_7_0 - Filter coefficients for the first set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX1_CHFLT_COE3_7_0 - Filter coefficients for the first set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX1_CHFLT_COE2_7_0 - Filter coefficients for the first set of RX filter coefficients.
|
||||
*/
|
||||
#define RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12 0x11, 0x21, 0x0C, 0x00, 0xFF, 0xC4, 0x30, 0x7F, 0xF5, 0xB5, 0xB8, 0xDE, 0x05, 0x17, 0x16, 0x0C
|
||||
|
||||
/*
|
||||
// Set properties: RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12
|
||||
// Number of properties: 12
|
||||
// Group ID: 0x21
|
||||
// Start ID: 0x0C
|
||||
// Default values: 0xFC, 0xFD, 0x15, 0xFF, 0x00, 0x0F, 0xFF, 0xC4, 0x30, 0x7F, 0xF5, 0xB5,
|
||||
// Descriptions:
|
||||
// MODEM_CHFLT_RX1_CHFLT_COE1_7_0 - Filter coefficients for the first set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX1_CHFLT_COE0_7_0 - Filter coefficients for the first set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX1_CHFLT_COEM0 - Filter coefficients for the first set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX1_CHFLT_COEM1 - Filter coefficients for the first set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX1_CHFLT_COEM2 - Filter coefficients for the first set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX1_CHFLT_COEM3 - Filter coefficients for the first set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX2_CHFLT_COE13_7_0 - Filter coefficients for the second set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX2_CHFLT_COE12_7_0 - Filter coefficients for the second set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX2_CHFLT_COE11_7_0 - Filter coefficients for the second set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX2_CHFLT_COE10_7_0 - Filter coefficients for the second set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX2_CHFLT_COE9_7_0 - Filter coefficients for the second set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX2_CHFLT_COE8_7_0 - Filter coefficients for the second set of RX filter coefficients.
|
||||
*/
|
||||
#define RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12 0x11, 0x21, 0x0C, 0x0C, 0x03, 0x00, 0x15, 0xFF, 0x00, 0x00, 0xFF, 0xC4, 0x30, 0x7F, 0xF5, 0xB5
|
||||
|
||||
/*
|
||||
// Set properties: RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12
|
||||
// Number of properties: 12
|
||||
// Group ID: 0x21
|
||||
// Start ID: 0x18
|
||||
// Default values: 0xB8, 0xDE, 0x05, 0x17, 0x16, 0x0C, 0x03, 0x00, 0x15, 0xFF, 0x00, 0x00,
|
||||
// Descriptions:
|
||||
// MODEM_CHFLT_RX2_CHFLT_COE7_7_0 - Filter coefficients for the second set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX2_CHFLT_COE6_7_0 - Filter coefficients for the second set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX2_CHFLT_COE5_7_0 - Filter coefficients for the second set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX2_CHFLT_COE4_7_0 - Filter coefficients for the second set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX2_CHFLT_COE3_7_0 - Filter coefficients for the second set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX2_CHFLT_COE2_7_0 - Filter coefficients for the second set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX2_CHFLT_COE1_7_0 - Filter coefficients for the second set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX2_CHFLT_COE0_7_0 - Filter coefficients for the second set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX2_CHFLT_COEM0 - Filter coefficients for the second set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX2_CHFLT_COEM1 - Filter coefficients for the second set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX2_CHFLT_COEM2 - Filter coefficients for the second set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX2_CHFLT_COEM3 - Filter coefficients for the second set of RX filter coefficients.
|
||||
*/
|
||||
#define RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12 0x11, 0x21, 0x0C, 0x18, 0xB8, 0xDE, 0x05, 0x17, 0x16, 0x0C, 0x03, 0x00, 0x15, 0xFF, 0x00, 0x00
|
||||
|
||||
/*
|
||||
// Set properties: RF_PA_MODE_4
|
||||
// Number of properties: 4
|
||||
// Group ID: 0x22
|
||||
// Start ID: 0x00
|
||||
// Default values: 0x08, 0x7F, 0x00, 0x5D,
|
||||
// Descriptions:
|
||||
// PA_MODE - Selects the PA operating mode, and selects resolution of PA power adjustment (i.e., step size).
|
||||
// PA_PWR_LVL - Configuration of PA output power level.
|
||||
// PA_BIAS_CLKDUTY - Configuration of the PA Bias and duty cycle of the TX clock source.
|
||||
// PA_TC - Configuration of PA ramping parameters.
|
||||
*/
|
||||
#define RF_PA_MODE_4 0x11, 0x22, 0x04, 0x00, 0x08, 0x7F, 0x00, 0x3D
|
||||
|
||||
/*
|
||||
// Set properties: RF_SYNTH_PFDCP_CPFF_7
|
||||
// Number of properties: 7
|
||||
// Group ID: 0x23
|
||||
// Start ID: 0x00
|
||||
// Default values: 0x2C, 0x0E, 0x0B, 0x04, 0x0C, 0x73, 0x03,
|
||||
// Descriptions:
|
||||
// SYNTH_PFDCP_CPFF - Feed forward charge pump current selection.
|
||||
// SYNTH_PFDCP_CPINT - Integration charge pump current selection.
|
||||
// SYNTH_VCO_KV - Gain scaling factors (Kv) for the VCO tuning varactors on both the integrated-path and feed forward path.
|
||||
// SYNTH_LPFILT3 - Value of resistor R2 in feed-forward path of loop filter.
|
||||
// SYNTH_LPFILT2 - Value of capacitor C2 in feed-forward path of loop filter.
|
||||
// SYNTH_LPFILT1 - Value of capacitors C1 and C3 in feed-forward path of loop filter.
|
||||
// SYNTH_LPFILT0 - Bias current of the active amplifier in the feed-forward loop filter.
|
||||
*/
|
||||
#define RF_SYNTH_PFDCP_CPFF_7 0x11, 0x23, 0x07, 0x00, 0x2C, 0x0E, 0x0B, 0x04, 0x0C, 0x73, 0x03
|
||||
|
||||
/*
|
||||
// Set properties: RF_FREQ_CONTROL_INTE_8
|
||||
// Number of properties: 8
|
||||
// Group ID: 0x40
|
||||
// Start ID: 0x00
|
||||
// Default values: 0x3C, 0x08, 0x00, 0x00, 0x00, 0x00, 0x20, 0xFF,
|
||||
// Descriptions:
|
||||
// FREQ_CONTROL_INTE - Frac-N PLL Synthesizer integer divide number.
|
||||
// FREQ_CONTROL_FRAC_2 - Frac-N PLL fraction number.
|
||||
// FREQ_CONTROL_FRAC_1 - Frac-N PLL fraction number.
|
||||
// FREQ_CONTROL_FRAC_0 - Frac-N PLL fraction number.
|
||||
// FREQ_CONTROL_CHANNEL_STEP_SIZE_1 - EZ Frequency Programming channel step size.
|
||||
// FREQ_CONTROL_CHANNEL_STEP_SIZE_0 - EZ Frequency Programming channel step size.
|
||||
// FREQ_CONTROL_W_SIZE - Set window gating period (in number of crystal reference clock cycles) for counting VCO frequency during calibration.
|
||||
// FREQ_CONTROL_VCOCNT_RX_ADJ - Adjust target count for VCO calibration in RX mode.
|
||||
*/
|
||||
#define RF_FREQ_CONTROL_INTE_8 0x11, 0x40, 0x08, 0x00, 0x3F, 0x0A, 0x5E, 0xD0, 0x4B, 0xDA, 0x20, 0xFE
|
||||
|
||||
|
||||
// AUTOMATICALLY GENERATED CODE!
|
||||
// DO NOT EDIT/MODIFY BELOW THIS LINE!
|
||||
// --------------------------------------------
|
||||
|
||||
#ifndef FIRMWARE_LOAD_COMPILE
|
||||
#define RADIO_CONFIGURATION_DATA_ARRAY { \
|
||||
0x07, RF_POWER_UP, \
|
||||
0x08, RF_GPIO_PIN_CFG, \
|
||||
0x06, RF_GLOBAL_XO_TUNE_2, \
|
||||
0x05, RF_GLOBAL_CONFIG_1, \
|
||||
0x06, RF_INT_CTL_ENABLE_2, \
|
||||
0x08, RF_FRR_CTL_A_MODE_4, \
|
||||
0x05, RF_PREAMBLE_TX_LENGTH_1, \
|
||||
0x05, RF_PREAMBLE_CONFIG_1, \
|
||||
0x07, RF_SYNC_CONFIG_3, \
|
||||
0x05, RF_PKT_CONFIG1_1, \
|
||||
0x05, RF_PKT_FIELD_1_CONFIG_1, \
|
||||
0x10, RF_MODEM_MOD_TYPE_12, \
|
||||
0x05, RF_MODEM_FREQ_DEV_0_1, \
|
||||
0x0C, RF_MODEM_TX_RAMP_DELAY_8, \
|
||||
0x0D, RF_MODEM_BCR_OSR_1_9, \
|
||||
0x0B, RF_MODEM_AFC_GEAR_7, \
|
||||
0x05, RF_MODEM_AGC_CONTROL_1, \
|
||||
0x0D, RF_MODEM_AGC_WINDOW_SIZE_9, \
|
||||
0x0C, RF_MODEM_OOK_CNT1_8, \
|
||||
0x05, RF_MODEM_RSSI_COMP_1, \
|
||||
0x05, RF_MODEM_CLKGEN_BAND_1, \
|
||||
0x10, RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12, \
|
||||
0x10, RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12, \
|
||||
0x10, RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12, \
|
||||
0x08, RF_PA_MODE_4, \
|
||||
0x0B, RF_SYNTH_PFDCP_CPFF_7, \
|
||||
0x0C, RF_FREQ_CONTROL_INTE_8, \
|
||||
0x00 \
|
||||
}
|
||||
#else
|
||||
#define RADIO_CONFIGURATION_DATA_ARRAY { 0 }
|
||||
#endif
|
||||
|
||||
// DEFAULT VALUES FOR CONFIGURATION PARAMETERS
|
||||
#define RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ_DEFAULT 30000000L
|
||||
#define RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER_DEFAULT 0x00
|
||||
#define RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH_DEFAULT 0x10
|
||||
#define RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP_DEFAULT 0x01
|
||||
#define RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET_DEFAULT 0x1000
|
||||
|
||||
#define RADIO_CONFIGURATION_DATA_RADIO_PATCH_INCLUDED 0x00
|
||||
#define RADIO_CONFIGURATION_DATA_RADIO_PATCH_SIZE 0x00
|
||||
#define RADIO_CONFIGURATION_DATA_RADIO_PATCH { }
|
||||
|
||||
#ifndef RADIO_CONFIGURATION_DATA_ARRAY
|
||||
#error "This property must be defined!"
|
||||
#endif
|
||||
|
||||
#ifndef RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ
|
||||
#define RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ_DEFAULT
|
||||
#endif
|
||||
|
||||
#ifndef RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER
|
||||
#define RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER_DEFAULT
|
||||
#endif
|
||||
|
||||
#ifndef RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH
|
||||
#define RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH_DEFAULT
|
||||
#endif
|
||||
|
||||
#ifndef RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP
|
||||
#define RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP_DEFAULT
|
||||
#endif
|
||||
|
||||
#ifndef RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET
|
||||
#define RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET_DEFAULT
|
||||
#endif
|
||||
|
||||
#define RADIO_CONFIGURATION_DATA { \
|
||||
Radio_Configuration_Data_Array, \
|
||||
RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER, \
|
||||
RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH, \
|
||||
RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP, \
|
||||
RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET \
|
||||
}
|
||||
|
||||
#endif /* RADIO_CONFIG_H_ */
|
||||
@ -0,0 +1,516 @@
|
||||
/*! @file radio_config.h
|
||||
* @brief This file contains the automatically generated
|
||||
* configurations.
|
||||
*
|
||||
* @n WDS GUI Version: 3.2.11.0
|
||||
* @n Device: Si4464 Rev.: B1
|
||||
*
|
||||
* @b COPYRIGHT
|
||||
* @n Silicon Laboratories Confidential
|
||||
* @n Copyright 2017 Silicon Laboratories, Inc.
|
||||
* @n http://www.silabs.com
|
||||
*/
|
||||
|
||||
#ifndef RADIO_CONFIG_H_
|
||||
#define RADIO_CONFIG_H_
|
||||
|
||||
// USER DEFINED PARAMETERS
|
||||
// Define your own parameters here
|
||||
|
||||
// INPUT DATA
|
||||
/*
|
||||
// Crys_freq(Hz): 30000000 Crys_tol(ppm): 20 IF_mode: 2 High_perf_Ch_Fil: 1 OSRtune: 0 Ch_Fil_Bw_AFC: 0 ANT_DIV: 0 PM_pattern: 0
|
||||
// MOD_type: 3 Rsymb(sps): 10000 Fdev(Hz): 20000 RXBW(Hz): 150000 Manchester: 0 AFC_en: 0 Rsymb_error: 0.0 Chip-Version: 3
|
||||
// RF Freq.(MHz): 434 API_TC: 29 fhst: 250000 inputBW: 0 BERT: 0 RAW_dout: 0 D_source: 0 Hi_pfm_div: 1
|
||||
//
|
||||
// # RX IF frequency is -468750 Hz
|
||||
// # WB filter 4 (BW = 82.64 kHz); NB-filter 4 (BW = 82.64 kHz)
|
||||
//
|
||||
// Modulation index: 4
|
||||
*/
|
||||
|
||||
|
||||
// CONFIGURATION PARAMETERS
|
||||
#define RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ 30000000L
|
||||
#define RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER 0x00
|
||||
#define RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH 0x07
|
||||
#define RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP 0x03
|
||||
#define RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET 0xF000
|
||||
|
||||
|
||||
// CONFIGURATION COMMANDS
|
||||
|
||||
/*
|
||||
// Command: RF_POWER_UP
|
||||
// Description: Command to power-up the device and select the operational mode and functionality.
|
||||
*/
|
||||
#define RF_POWER_UP 0x02, 0x01, 0x00, 0x01, 0xC9, 0xC3, 0x80
|
||||
|
||||
/*
|
||||
// Command: RF_GPIO_PIN_CFG
|
||||
// Description: Configures the GPIO pins.
|
||||
*/
|
||||
#define RF_GPIO_PIN_CFG 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
|
||||
|
||||
/*
|
||||
// Set properties: RF_GLOBAL_XO_TUNE_2
|
||||
// Number of properties: 2
|
||||
// Group ID: 0x00
|
||||
// Start ID: 0x00
|
||||
// Default values: 0x40, 0x00,
|
||||
// Descriptions:
|
||||
// GLOBAL_XO_TUNE - Configure the internal capacitor frequency tuning bank for the crystal oscillator.
|
||||
// GLOBAL_CLK_CFG - Clock configuration options.
|
||||
*/
|
||||
#define RF_GLOBAL_XO_TUNE_2 0x11, 0x00, 0x02, 0x00, 0x52, 0x00
|
||||
|
||||
/*
|
||||
// Set properties: RF_GLOBAL_CONFIG_1
|
||||
// Number of properties: 1
|
||||
// Group ID: 0x00
|
||||
// Start ID: 0x03
|
||||
// Default values: 0x20,
|
||||
// Descriptions:
|
||||
// GLOBAL_CONFIG - Global configuration settings.
|
||||
*/
|
||||
#define RF_GLOBAL_CONFIG_1 0x11, 0x00, 0x01, 0x03, 0x60
|
||||
|
||||
/*
|
||||
// Set properties: RF_INT_CTL_ENABLE_2
|
||||
// Number of properties: 2
|
||||
// Group ID: 0x01
|
||||
// Start ID: 0x00
|
||||
// Default values: 0x04, 0x00,
|
||||
// Descriptions:
|
||||
// INT_CTL_ENABLE - This property provides for global enabling of the three interrupt groups (Chip, Modem and Packet Handler) in order to generate HW interrupts at the NIRQ pin.
|
||||
// INT_CTL_PH_ENABLE - Enable individual interrupt sources within the Packet Handler Interrupt Group to generate a HW interrupt on the NIRQ output pin.
|
||||
*/
|
||||
#define RF_INT_CTL_ENABLE_2 0x11, 0x01, 0x02, 0x00, 0x01, 0x20
|
||||
|
||||
/*
|
||||
// Set properties: RF_FRR_CTL_A_MODE_4
|
||||
// Number of properties: 4
|
||||
// Group ID: 0x02
|
||||
// Start ID: 0x00
|
||||
// Default values: 0x01, 0x02, 0x09, 0x00,
|
||||
// Descriptions:
|
||||
// FRR_CTL_A_MODE - Fast Response Register A Configuration.
|
||||
// FRR_CTL_B_MODE - Fast Response Register B Configuration.
|
||||
// FRR_CTL_C_MODE - Fast Response Register C Configuration.
|
||||
// FRR_CTL_D_MODE - Fast Response Register D Configuration.
|
||||
*/
|
||||
#define RF_FRR_CTL_A_MODE_4 0x11, 0x02, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00
|
||||
|
||||
/*
|
||||
// Set properties: RF_PREAMBLE_TX_LENGTH_1
|
||||
// Number of properties: 1
|
||||
// Group ID: 0x10
|
||||
// Start ID: 0x00
|
||||
// Default values: 0x08,
|
||||
// Descriptions:
|
||||
// PREAMBLE_TX_LENGTH - Configure length of TX Preamble.
|
||||
*/
|
||||
#define RF_PREAMBLE_TX_LENGTH_1 0x11, 0x10, 0x01, 0x00, 0x0A
|
||||
|
||||
/*
|
||||
// Set properties: RF_PREAMBLE_CONFIG_1
|
||||
// Number of properties: 1
|
||||
// Group ID: 0x10
|
||||
// Start ID: 0x04
|
||||
// Default values: 0x21,
|
||||
// Descriptions:
|
||||
// PREAMBLE_CONFIG - General configuration bits for the Preamble field.
|
||||
*/
|
||||
#define RF_PREAMBLE_CONFIG_1 0x11, 0x10, 0x01, 0x04, 0x31
|
||||
|
||||
/*
|
||||
// Set properties: RF_SYNC_CONFIG_3
|
||||