add fpga config

pull/56/head
ua1arn 2021-11-09 19:01:45 +03:00
parent abb6dfc2e7
commit 54c8e4a15c
6 changed files with 25079 additions and 15 deletions

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@ -18,27 +18,28 @@
#
# Quartus II 64-Bit
# Version 13.1.4 Build 182 03/12/2014 SJ Full Version
# Date created = 05:43:05 August 18, 2020
# Date created = 17:01:30 November 09, 2021
#
# -------------------------------------------------------------------------- #
QUARTUS_VERSION = "13.1"
DATE = "05:43:05 August 18, 2020"
DATE = "17:01:30 November 09, 2021"
# Revisions
PROJECT_REVISION = "t1_v9c_2ch"
PROJECT_REVISION = "t1_v8t_96k"
PROJECT_REVISION = "t1_v4_pll"
PROJECT_REVISION = "t1_v5_2ch_pll"
PROJECT_REVISION = "t1_v4"
PROJECT_REVISION = "t1_v7_1ch"
PROJECT_REVISION = "t1_v3"
PROJECT_REVISION = "t1_v9a_2ch"
PROJECT_REVISION = "t1_v8t_192k"
PROJECT_REVISION = "t1_v3_pll"
PROJECT_REVISION = "t1_v6_2ch"
PROJECT_REVISION = "t1_v5_2ch"
PROJECT_REVISION = "t1_v7_oleg4z"
PROJECT_REVISION = "t1_v7_2ch"
PROJECT_REVISION = "t1_v7h_2ch"
PROJECT_REVISION = "t1_v7a_2ch"
PROJECT_REVISION = "t1_v7h_2ch"
PROJECT_REVISION = "t1_v7_2ch"
PROJECT_REVISION = "t1_v7_oleg4z"
PROJECT_REVISION = "t1_v5_2ch"
PROJECT_REVISION = "t1_v6_2ch"
PROJECT_REVISION = "t1_v3_pll"
PROJECT_REVISION = "t1_v8t_192k"
PROJECT_REVISION = "t1_v3"
PROJECT_REVISION = "t1_v7_1ch"
PROJECT_REVISION = "t1_v4"
PROJECT_REVISION = "t1_v5_2ch_pll"
PROJECT_REVISION = "t1_v4_pll"
PROJECT_REVISION = "t1_v9a_2ch"

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# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2014 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 13.1.4 Build 182 03/12/2014 SJ Full Version
# Date created = 02:46:03 December 04, 2015
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# t1_v9c_2ch_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
# Project-Wide Assignments
# ========================
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "17:01:27 NOVEMBER 09, 2021"
set_global_assignment -name LAST_QUARTUS_VERSION 13.1
set_global_assignment -name SMART_RECOMPILE ON
# Pin & Location Assignments
# ==========================
set_location_assignment PIN_90 -to refclk_in
set_location_assignment PIN_126 -to adc_clka
set_location_assignment PIN_125 -to adc_data[0]
set_location_assignment PIN_121 -to adc_data[1]
set_location_assignment PIN_120 -to adc_data[2]
set_location_assignment PIN_119 -to adc_data[3]
set_location_assignment PIN_115 -to adc_data[4]
set_location_assignment PIN_114 -to adc_data[5]
set_location_assignment PIN_113 -to adc_data[6]
set_location_assignment PIN_112 -to adc_data[7]
set_location_assignment PIN_111 -to adc_data[8]
set_location_assignment PIN_110 -to adc_data[9]
set_location_assignment PIN_106 -to adc_data[10]
set_location_assignment PIN_105 -to adc_data[11]
set_location_assignment PIN_104 -to adc_data[12]
set_location_assignment PIN_103 -to adc_data[13]
set_location_assignment PIN_101 -to adc_data[14]
set_location_assignment PIN_100 -to adc_data[15]
set_location_assignment PIN_99 -to adc_ovfl
set_location_assignment PIN_86 -to adc_pga
set_location_assignment PIN_72 -to dac_d[13]
set_location_assignment PIN_71 -to dac_d[12]
set_location_assignment PIN_69 -to dac_d[11]
set_location_assignment PIN_68 -to dac_d[10]
set_location_assignment PIN_67 -to dac_d[9]
set_location_assignment PIN_59 -to dac_d[4]
set_location_assignment PIN_58 -to dac_d[3]
set_location_assignment PIN_51 -to dac_d[2]
set_location_assignment PIN_50 -to dac_d[1]
set_location_assignment PIN_49 -to dac_d[0]
set_location_assignment PIN_46 -to dac_sleep
set_location_assignment PIN_66 -to dac_d[8]
set_location_assignment PIN_65 -to dac_d[7]
set_location_assignment PIN_64 -to dac_d[6]
set_location_assignment PIN_60 -to dac_d[5]
set_location_assignment PIN_33 -to sai1_sd_a
set_location_assignment PIN_32 -to sai1_sck_a
set_location_assignment PIN_31 -to sai1_fs_a
set_location_assignment PIN_30 -to sai1_sd_b
set_location_assignment PIN_13 -to cpu_mosi
set_location_assignment PIN_24 -to fpga_ctl_cs
set_location_assignment PIN_6 -to cpu_miso
set_location_assignment PIN_12 -to cpu_sclk
set_location_assignment PIN_132 -to adc_shdn
set_location_assignment PIN_133 -to adc_dith
set_location_assignment PIN_137 -to tx_inh_h
set_location_assignment PIN_8 -to fpga_fir1_we_n
set_location_assignment PIN_7 -to fpga_fir2_we_n
set_location_assignment PIN_39 -to led0
set_location_assignment PIN_42 -to led1
set_location_assignment PIN_129 -to pps_in
set_location_assignment PIN_43 -to led2
set_location_assignment PIN_44 -to led3
# Classic Timing Assignments
# ==========================
set_global_assignment -name MIN_CORE_JUNCTION_TEMP "-40"
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
# Analysis & Synthesis Assignments
# ================================
set_global_assignment -name FAMILY "Cyclone IV E"
set_global_assignment -name TOP_LEVEL_ENTITY tc1_top_v9c_2ch
# Fitter Assignments
# ==================
set_global_assignment -name DEVICE EP4CE22E22I7
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVCMOS"
set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF
set_global_assignment -name ENABLE_NCE_PIN OFF
set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF
set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON
set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON
# Assembler Assignments
# =====================
set_global_assignment -name USE_CONFIGURATION_DEVICE ON
set_global_assignment -name GENERATE_RBF_FILE ON
set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE EPCS16
# Power Estimation Assignments
# ============================
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
# Advanced I/O Timing Assignments
# ===============================
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
# ----------------------------
# start ENTITY(tc1_top_v5_2ch)
# Pin & Location Assignments
# ==========================
# Fitter Assignments
# ==================
# start DESIGN_PARTITION(Top)
# ---------------------------
# Incremental Compilation Assignments
# ===================================
# end DESIGN_PARTITION(Top)
# -------------------------
# end ENTITY(tc1_top_v5_2ch)
# --------------------------
set_location_assignment PIN_28 -to fpga_ovf
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to dac_sleep -disable
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to cpu_miso -disable
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to cpu_mosi -disable
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to cpu_sclk -disable
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to adc_ovfl -disable
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to adc_pga -disable
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to adc_rand -disable
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to adc_shdn -disable
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to adc_dith -disable
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to dac_d -disable
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to fpga_nco_cs -disable
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to refclk_in -disable
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sai1_fs_a -disable
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sai1_sck_a -disable
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sai1_sd_a -disable
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sai1_sd_b -disable
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to adc_clka -disable
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to adc_data* -disable
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to tx_inh_h -disable
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to fpga_fir1_we_n -disable
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to fpga_fir2_we_n -disable
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to fpga_ctl_cs -disable
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to fpga_fir_clk_n -disable
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to pps_in -disable
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to led0 -disable
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to led1 -disable
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to i2s2_ws -disable
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to i2s2_ck -disable
set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "1 MHz" -to pps_in -disable
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to dac_clk_alt -disable
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to led2 -disable
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to led3 -disable
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to dac_d* -disable
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON
set_global_assignment -name ENABLE_INIT_DONE_OUTPUT ON
set_location_assignment PIN_23 -to fpga_fir_cs
set_global_assignment -name QIP_FILE lpm_counter_mod6.qip
set_global_assignment -name QIP_FILE lpm_counter_i2sclocls.qip
set_global_assignment -name QIP_FILE lpm_shiftreg_32.qip
set_global_assignment -name QIP_FILE lpm_counter1.qip
set_global_assignment -name QIP_FILE lpm_shiftreg_2b.qip
set_global_assignment -name QIP_FILE mult16.qip
set_global_assignment -name QIP_FILE ducadd.qip
set_global_assignment -name QIP_FILE ducmult1.qip
set_global_assignment -name QIP_FILE nco18_v13.qip
set_global_assignment -name QIP_FILE cicdec0.qip
set_global_assignment -name QIP_FILE lpm_counter_ovf0.qip
set_global_assignment -name QIP_FILE cic_duc2560_mux.qip
set_global_assignment -name QIP_FILE lpm_decode_4ch.qip
set_global_assignment -name QIP_FILE lpm_decode_2ch.qip
set_global_assignment -name QIP_FILE dacout14.qip
set_global_assignment -name QIP_FILE lpm_decode_4ch_en.qip
set_global_assignment -name QIP_FILE fifo64.qip
set_global_assignment -name QIP_FILE cic_64_2iq.qip
set_global_assignment -name QIP_FILE cic40_ddc_2rx.qip
set_global_assignment -name QIP_FILE fir_20_2ch.qip
set_global_assignment -name QIP_FILE clkctrl1.qip
set_global_assignment -name QIP_FILE lpm_counter_mod24.qip
set_global_assignment -name BDF_FILE ctlbridge.bdf
set_global_assignment -name BDF_FILE LTC2208_input_fifo.bdf
set_global_assignment -name BDF_FILE LTC2208_input.bdf
set_global_assignment -name BDF_FILE DAC_interface.bdf
set_global_assignment -name BDF_FILE i2s_sync.bdf
set_global_assignment -name BDF_FILE i2smclk.bdf
set_global_assignment -name BDF_FILE spislave_sync.bdf
set_global_assignment -name BDF_FILE monoflop_ovf.bdf
set_global_assignment -name BDF_FILE ddc_mux.bdf
set_global_assignment -name BDF_FILE duc_mux.bdf
set_global_assignment -name BDF_FILE i2s_rx_slave.bdf
set_global_assignment -name BDF_FILE fqmemter.bdf
set_global_assignment -name BDF_FILE t1_2ch_rts96.bdf
set_global_assignment -name QIP_FILE adcoffset16.qip
set_global_assignment -name QIP_FILE cic_128a_3iq.qip
set_global_assignment -name QIP_FILE cic20a_ddc_2rx.qip
set_global_assignment -name QIP_FILE fir_10a_2ch.qip
set_global_assignment -name QIP_FILE cic_128a_2iq.qip
set_global_assignment -name QIP_FILE fir_5a_2ch.qip
set_location_assignment PIN_83 -to pll_out
set_location_assignment PIN_144 -to i2s2_ws
set_location_assignment PIN_142 -to i2s2_ck
set_location_assignment PIN_76 -to sai2_sd_b
set_location_assignment PIN_77 -to sai2_fs_a
set_location_assignment PIN_80 -to sai2_sck_a
set_global_assignment -name QIP_FILE dacout15.qip
set_global_assignment -name QIP_FILE lpm_counter_ovf_1024.qip
set_global_assignment -name BDF_FILE tc1_top_v9c_2ch.bdf
set_global_assignment -name SDC_FILE tc1_top_v9c_2ch.sdc
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_instance_assignment -name FAST_INPUT_REGISTER ON -to adc_ovfl
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to dac_d
set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "1 MHz" -to adc_pga
set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "1 MHz" -to adc_shdn
set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "10 MHz" -to cpu_miso
set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "1 MHz" -to dac_sleep
set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "5 MHz" -to sai1_sd_b
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to i2s2_mck
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to i2s2_ck
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to sai1_sck_a
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to sai1_fs_a
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to i2s2_ws
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to sai1_sd_b
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to dac_d*
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to adc_ovfl
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to tx_inh_h
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to adc_d*
set_location_assignment PIN_143 -to i2s_ckin
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

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#************************************************************
# THIS IS A WIZARD-GENERATED FILE.
#
# Version 13.1.4 Build 182 03/12/2014 SJ Full Version
#
#************************************************************
# Copyright (C) 1991-2014 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
#************************************************************
# THIS IS A WIZARD-GENERATED FILE.
#
# Version 11.1 Build 259 01/25/2012 Service Pack 2 SJ Full Version
#
#************************************************************
# Automatically calculate clock uncertainty to jitter and other effects.
derive_clock_uncertainty
# Automatically constrain PLL and other generated clocks
derive_pll_clocks -create_base_clocks
create_clock -name "clockfromadc" -period 125MHz [get_ports {adc_clka}]
create_clock -name "ref122880" -period 125MHz [get_ports {refclk_in}]
#create_generated_clock -name "i2s2_mck" -source [get_ports {refclk_in}] -divide_by 10 -duty_cycle 40.0 [get_ports {i2s2_mck}]
create_clock -name "sclk_clock" -period 25MHz [get_ports {cpu_sclk}]
create_clock -name "fpga_ctl_cs_clock" -period 25MHz [get_ports {fpga_ctl_cs}]
#create_clock -name "fpga_fir_cs_clock" -period 25MHz [get_ports {fpga_fir_cs}]
#create_clock -name "sai1_sck_a_clock" -period 13MHz [get_ports {sai1_sck_a}]
#create_generated_clock -name "sai1_sck_a_clock" -source [get_ports {refclk_in}] -divide_by 10 -duty_cycle 40.0 [get_ports {sai1_sck_a}]
set_clock_groups -exclusive \
-group { [get_clocks {clockfromadc}] [get_clocks {ref122880}] } \
-group { [get_clocks {i2s2_mck}] } \
-group { [get_clocks {sai1_sck_a_clock}] } \
-group { [get_clocks {sclk_clock}] } \
-group { [get_clocks {fpga_ctl_cs_clock}] } \
# -group { [get_clocks {fpga_fir_cs_clock}] }
set_false_path -from [get_clocks { ref122880 }] -to [get_ports {adc_dith adc_rand adc_shdn adc_pga dac_sleep}]
set_false_path -from [get_clocks { ref122880 }] -to [get_ports {led0 led1 led2 led3 fpga_ovf}]
set_false_path -from [get_clocks { ref122880 }] -to [get_ports {sai1_sd_b}]
set_false_path -from [get_clocks { ref122880 }] -to [get_ports {i2s2_mck}]
set_false_path -from [get_clocks { ref122880 }] -to [get_ports {sai1_sck_a}]
set_false_path -from [get_clocks { ref122880 }] -to [get_ports {refclk_out}]
# tsu/th constraints
# tco constraints
# tpd constraints
#set_input_delay -clock "clockfromadc" -min [expr { - 0.8}] [get_ports {adc_data[*] adc_ovfl}]
#set_input_delay -clock "clockfromadc" -max [expr { + 0.8}] [get_ports {adc_data[*] adc_ovfl}]
#**************************************************************
# Set Clock Latency
#**************************************************************
set_output_delay -clock [get_clocks {ref122880}] -max 36ps [get_ports {dac_d[*]}]
set_output_delay -clock [get_clocks {ref122880}] -min 30ps [get_ports {dac_d[*]}]
#**************************************************************
# Set Input Delay
#**************************************************************
set_input_delay -clock clockfromadc -max 0ps [get_ports adc_data[*]]
set_input_delay -clock clockfromadc -min -66ps [get_ports adc_data[*]]
set_input_delay -clock clockfromadc -max 0ps [get_ports adc_ovfl]
set_input_delay -clock clockfromadc -min -66ps [get_ports adc_ovfl]

23271
rbf/rbfimage_v9c_2ch.h 100644

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@ -16,5 +16,6 @@ rbf2c.exe %SRCPATH%\t1_v7_oleg4z.rbf ..\rbf\rbfimage_oleg4z.h
rbf2c.exe %SRCPATH%\t1_v8t_96k.rbf ..\rbf\rbfimage_v8t_96k.h
rbf2c.exe %SRCPATH%\t1_v8t_192k.rbf ..\rbf\rbfimage_v8t_192k.h
rbf2c.exe %SRCPATH%\t1_v9a_2ch.rbf ..\rbf\rbfimage_v9a_2ch.h
rbf2c.exe %SRCPATH%\t1_v9c_2ch.rbf ..\rbf\rbfimage_v9c_2ch.h
pause